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LTC1454/LTC1454L Dual 12-Bit Rail-to-Rail Micropower DACs
FEATURES
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DESCRIPTION
The LTC(R)1454/LTC1454L are complete single supply, dual rail-to-rail voltage output, 12-bit digital-to-analog converters (DACs) in a 16-lead SO package. They include an output buffer amplifier with variable gain (x1 or x 2) and an easy-to-use 3-wire cascadable serial interface. The LTC1454 has an onboard reference of 2.048V and a full-scale output of 4.095V in a x 2 gain configuration. It operates from a single 4.5V to 5.5V supply. The LTC1454L has an onboard 1.22V reference and a fullscale output of 2.5V in a x 2 gain configuration. It operates from a single 2.7V to 5.5V supply. Low power supply current, excellent DNL and small size allow these parts to be used in a host of applications where size, DNL and single supply operation are important.
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12-Bit Resolution Buffered True Rail-to-Rail Voltage Output 5V Operation, ICC: 700A Typ (LTC1454) 3V Operation, ICC: 450A Typ (LTC1454L) Built-In Reference: 2.048V (LTC1454) 1.220V (LTC1454L) CLR Pin Power-On Reset 16-Lead SO Package 3-Wire Cascadable Serial Interface Maximum DNL Error: 0.5LSB Low Cost
APPLICATIONS
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Digital Calibration Industrial Process Control Automatic Test Equipment Cellular Telephones
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
Daisy-Chained Dual 12-Bit Rail-to-Rail DAC Functional Block Diagram: Control Outputs
LTC1454: 5V LTC1454L: 3V TO 5V 9, 15 VCC LTC1454: 2.048V 10 LTC1454L: 1.22V REFOUT REFHI B 14
0.5 0.4 0.3
DNL ERROR (LSB)
+
4 DIN P 3 CLK 5 CS/LD 6 DOUT 12-BIT DAC B 24-BIT SHIFT REG AND DAC LATCH
VOUT B 16
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 512 1024 1536 2048 2560 3072 3584 4095 CODE
1454 G08
-
X1/X2 B 1 REFHI A 11
+
12-BIT DAC A
VOUT A 8
-
X1/X2 A 7
POWER-ON RESET CLR 2 12 REFLO GND 13
1454 BD02
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Differential Nonlinearity vs Input Code
1
LTC1454/LTC1454L ABSOLUTE MAXIMUM RATINGS
VCC to GND .............................................. - 0.5V to 7.5V Logic Inputs to GND ................................ - 0.5V to 7.5V VOUT A , VOUT B, X1/X2 A , X1/X2 B ..................................... - 0.5V to VCC + 0.5V REFHI A , REFHI B, REFLO ............. - 0.5V to VCC + 0.5V Maximum Junction Temperature .......................... 125C Operating Temperature Range LTC1454C/LTC1454LC ............................ 0C to 70C LTC1454I/LTC1454LI ........................ - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
PACKAGE/ORDER I FOR ATIO
TOP VIEW X1/X2 B 1 CLR 2 CLK 3 DIN 4 CS/LD 5 DOUT 6 X1/X2 A 7 VOUT A 8 16 VOUT B 15 VCC 14 REFHI B 13 GND 12 REFLO 11 REFHI A 10 REFOUT 9 VCC
ORDER PART NUMBER LTC1454CN LTC1454IN LTC1454CS LTC1454IS LTC1454LCN LTC1454LIN LTC1454LCS LTC1454LIS
N PACKAGE S PACKAGE 16-LEAD PDIP 16-LEAD PLASTIC SO TJMAX = 125C, JA = 100C/W (N) TJMAX = 125C, JA = 150C/W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 4.5V to 5.5V (LTC1454), 2.7V to 5.5V (LTC1454L), X1/X2 = REFLO = GND, REFHI = REFOUT, VOUT and REFOUT unloaded, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL DAC Resolution DNL INL VOS VOSTC VFS Differential Nonlinearity Integral Nonlinearity Offset Error Offset Error Temperature Coefficient Full-Scale Voltage When Using Internal Reference, LTC1454, TA = 25C LTC1454 When Using Internal Reference, LTC1454L, TA = 25C LTC1454L VFSTC Reference Reference Output Voltage Reference Output Temperature Coefficient Reference Line Regulation Reference Load Regulation Reference Input Range Reference Input Resistance Reference Input Capacitance Short-Circuit Current REFOUT Shorted to GND
q q q q q
PARAMETER
CONDITIONS
MIN 12
TYP
MAX
UNITS Bits
Guaranteed Monotonic (Note 1) TA = 25C (Note 1) TA = 25C
q q q
0.5 2.0 2.5 2.0 4.0 15 4.065 4.045 2.470 2.460 4.095 4.095 2.500 2.500 24 4.125 4.145 2.530 2.540 4.0 4.5 12 18
V/C V V V V ppm/C
Full-Scale Voltage Temperature Coefficient
When Using Internal Reference
LTC1454 LTC1454L
q q
2.008 1.195
2.048 1.220 20 0.7 0.2 0.6 VCC / 2
2.088 1.245
ppm/C 2.0 1.5 3.0 40 120 LSB/V LSB LSB V k pF mA
0 IOUT 100A, LTC1454 LTC1454L VREFHI VCC - 1.5V
q q
q
15
24 15 40
2
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LSB LSB LSB mV mV V V
W
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WW
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LTC1454/LTC1454L
ELECTRICAL CHARACTERISTICS
VCC = 4.5V to 5.5V (LTC1454), 2.7V to 5.5V (LTC1454L), X1/X2 = REFLO = GND, REFHI = REFOUT, VOUT and REFOUT unloaded, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL VCC ICC PARAMETER Positive Supply Voltage Supply Current CONDITIONS For Specified Performance, LTC1454 LTC1454L 4.5V VCC 5.5V (Note 4), LTC1454 2.7V VCC 5.5V (Note 4), LTC1454L VOUT Shorted to GND VOUT Shorted to VCC Input Code = 0 (Note 2) (Notes 2, 3) to 0.5LSB REFHI = 1kHz, 2VP-P, (Code: All 0s) REFHI = 1kHz, 2VP-P, (Code: All 1s)
q q q q
MIN 4.5 2.7
TYP
MAX 5.5 5.5
UNITS V V A A mA mA V/s s nV * s dB dB
Power Supply
700 450 70 80 40 0.5 1.0 14 0.3 - 95 85
1250 1100 120 120
Op Amp DC Performance Short-Circuit Current Low Short-Circuit Current High Output Impedance to GND AC Performance Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough AC Feedthrough SINAD Signal-to-Noise + Distortion
q q q q
VCC = 5V (LTC1454), 3V (LTC1454L), TA = TMIN to TMAX, unless otherwise noted. SYMBOL Digital I/O VIH VIL VOH VOL ILEAK CIN Switching t1 t2 t3 t4 t5 t6 t7 t8 t9 DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low CLOAD = 15pF
q q q q q q q q q
PARAMETER Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance
CONDITIONS
q q
MIN 2.4
LTC1454 TYP MAX
MIN 2.0
LTC1454L TYP MAX
UNITS V
0.8 VCC - 1.0 0.4 10 10 40 0 40 40 50 40 20 150 20 30 60 0 60 60 80 60 30 VCC - 0.7
0.6 0.4 10 10
V V V A pF ns ns ns ns ns ns ns
IOUT = - 1mA IOUT = 1mA VIN = GND to VCC Guaranteed by Design
q q q q
220
ns ns
The q denotes specifications which apply over the full operating temperature range. Note 1: Nonlinearity is defined from the first code that is greater than or equal to the maximum offset specification to code 4095 (full scale).
Note 2: Load is 5k in parallel with 100pF. Note 3: DAC switched between all 1s and the code corresponding to VOS for the part. Note 4: Digital inputs at 0V or VCC.
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LTC1454/LTC1454L TYPICAL PERFORMANCE CHARACTERISTICS
LTC1454 Differential Nonlinearity
0.5 0.4 0.3 2.0 1.6 1.2
INL ERROR (LSB)
DNL ERROR (LSB)
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 512 1024 1536 2048 2560 3072 3584 4095 CODE
1454 G08
VCC - VOUT (V)
LTC1454 Minimum Output Voltage vs Output Sink Current
1000
OUTPUT PULL-DOWN VOLTAGE (mV)
900 800 700 600 500 400 300 200 100 0.1 0
REFLO = GND X1/X2 = GND
125C
25C
OUTPUT SWING (V)
OUTPUT SWING (V)
5
10 15 20 25 OUTPUT SINK CURRENT (mA)
LTC1454 Full-Scale Voltage vs Temperature
4.110 4.105
SFULL-SCALE VOLTAGE (V)
SUPPLY CURRENT (A)
740 730 720 710 700 690 -55
VCC = 5.5V
4.100 4.095 4.090 4.085 4.080 -55
SUPPLY CURRENT (mA)
-25
5 35 65 TEMPERATURE (C)
4
UW
-55C
1454 G04
LTC1454 Integral Nonlinearity
1.0
Minimum Supply Headroom for Full Output Swing vs Load Current
VOUT < 1LSB REFLO = GND X1/X2 = GND CODE: ALL 1's VOUT = 4.095V
0.8
0.8 0.4 0 -0.4 -0.8 -1.2 -1.6 -2.0 0 512 1024 1536 2048 2560 3072 3584 4095 CODE
1454 G07
0.6
0.4
0.2
0 0 5 10 15 20 LOAD CURRENT (mA) 25 30
1454 G03
LTC1454 Output Swing vs Load Resistance
4.5 4.0 3.5 3.0 2.5 2.0
RL
LTC1454 Output Swing vs Load Resistance
4.5 4.0 3.5 3.0
VCC
REFLO = GND X1/X2 = GND
REFLO = GND X1/X2 = GND
2.5 2.0 1.5 1.0 0.5 0
RL
1.5 1.0 0.5
30
0 10 100 1k LOAD RESISTANCE () 10k
1454 G05
10
100 1k LOAD RESISTANCE ()
10k
1458 G06
LTC1454 Supply Current vs Temperature
760 750
2.1 2.6
LTC1454 Supply Current vs Logic Input Voltage
1.6
VCC = 5V
1.1
VCC = 4.5V
0.6
95
125
1454 G02
-25
35 65 5 TEMPERATURE (C)
95
125
1454 G01
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOGIC INPUT VOLTAGE (V)
1454 G09
LTC1454/LTC1454L
PIN FUNCTIONS
X1/X2 B, X1/X2 A (Pins 1, 7): The Input Pin that Sets the Gain for DAC A/B. When grounded the gain will be 2, i.e., output full scale will be x 2 REFHI. When connected to VOUT the gain will be 1, i.e., output full scale will be equal to REFHI. CLR (Pin 2): The Clear Pin for the DAC. Clears both DACs to zero scale when pulled low. This pin should be tied to VCC for normal operation. CLK (Pin 3): The Serial Interface Clock Input. DIN (Pin 4): The Serial Data Input. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. Data is loaded as one 24-bit word. The first 12 bits are for DAC A, MSB-first and the second 12 bits are for DAC B, MSB-first. CS/LD (Pin 5): The Serial Interface Enable and Load Control Input. When CS/LD is low the CLK signal is enabled so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output. DOUT (Pin 6): The Output of the Shift Register which Becomes Valid on the Rising Edge of the Serial Clock. VOUT A, VOUT B (Pins 8, 16): The Buffered DAC Outputs. VCC (Pins 9, 15): The Positive Supply Input. 4.5 VCC 5.5V (LTC1454), 2.7V VCC 5.5V (LTC1454L). Requires a bypass capacitor to ground. REFOUT (Pin 10): The Output of the Internal Reference. REFHI A , REFHI B (Pins 11,14): The Inputs to the DAC Resistor Ladder for DAC A/B. REFLO (Pin 12): The Bottom of the DAC Resistor Ladder for Both DACs. This can be used to offset zero-scale above ground. REFLO should be connected to ground when no offset is required. GND (Pin 13): Ground.
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5
LTC1454/LTC1454L
BLOCK DIAGRA
X1/X2 B 1 2
CLR
CLK
3
DAC B
CS/LD
5
24-BIT SHIFT REGISTER LD 12-BIT DAC A REGISTER POWER-ON RESET R DAC A
DOUT
6
X1/X2 A
7
-
R
VOUT A
8
TI I G DIAGRA
t9 CLK
t1
t2
t4
t3
DIN
B0 B PREVIOUS WORD
B11 A MSB
B0 A LSB
B11 B MSB
CS/LD
t8
DOUT
B11 A PREVIOUS WORD
B10 A PREVIOUS WORD
B0 A PREVIOUS WORD
B11 B PREVIOUS WORD
6
+
DIN
4
LD 12-BIT DAC B REGISTER
-
W
W
R R 16 VOUT B VCC 15 14 REFHI B B 13 GND 12 REFLO 11 REFHI A
+
A REFERENCE LTC1454: 2.048V LTC1454L: 1.22V 10 REFOUT
9
VCC
1454 BD01
UW
t6
t7
B0 B LSB
t5
B0 B PREVIOUS WORD
B11 A CURRENT WORD
1454/5 * TD01
LTC1454/LTC1454L
DEFI ITIO S
Resolution (n): Resolution is defined as the number of digital input bits, n. It defines the number of DAC output states (2n) that divide the full-scale range. The resolution does not imply linearity. Full-Scale Voltage (VFS): This is the output of the DAC when all bits are set to 1. Voltage Offset Error (VOS): The theoretical voltage at the output when the DAC is loaded with all zeros. The output amplifier can have a true negative offset, but because the part is operated from a single supply, the output cannot go below zero. If the offset is negative, the output will remain near 0V resulting in the transfer curve shown in Figure 1.
OUTPUT VOLTAGE
NEGATIVE OFFSET
0V
Figure 1. Effect of Negative Offset
The offset of the part is measured at the code that corresponds to the maximum offset specification: VOS = VOUT - (Code)(VFS)/(2n - 1) Least Significant Bit (LSB): One LSB is the ideal voltage difference between two successive codes.
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LSB = (VFS - VOS)/(2n - 1) = (VFS - VOS)/4095 Nominal LSBs: LTC1454 LTC1454L LSB = 4.095V/4095 = 1mV LSB = 2.5V/4095 = 0.610mV
Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the end-points of the DAC transfer curve. Because the part operates from a single supply and the output cannot go below zero, the linearity is measured between full scale and the code corresponding to the maximum offset specification. The INL error at a given input code is calculated as follows: INL = [VOUT - VOS - (VFS - VOS)(Code/4095)]/LSB VOUT = The output voltage of the DAC measured at the given input code
DAC CODE
LTC1454/5 * F01
Differential Nonlinearity (DNL): DNL is the difference between the measured change and the ideal 1LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (VOUT - LSB)/LSB VOUT = The measured voltage difference between two adjacent codes Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec).
7
LTC1454/LTC1454L
OPERATIO
Serial Interface
The data on the DIN input is loaded into the shift register on the rising edge of the clock. Data is loaded as one 24-bit word, DAC A first, then DAC B. The MSB is loaded first for each DAC. The DAC registers load the data from the shift register when CS/LD is pulled high. The CLK is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. The buffered output of the 24-bit shift register is available on the DOUT pin which swings from ground to VCC. Multiple LTC1454/LTC1454Ls may be daisy-chained together by connecting the DOUT pin to the DIN pin of the next chip, while the CLK and CS/LD signals remain common to all chips in the daisy-chain. The serial data is clocked to all of the chips, then the CS/LD signal is pulled high to update all of them simultaneously.
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Reference The LTC1454L has an internal reference of 1.22V with a full scale of 2.5V (gain of 2 configuration). The LTC1454 includes an internal 2.048V reference, making 1LSB equal to 1mV (gain of 2 configuration). When the buffer gain is 2, the external reference must be less than VCC /2 and be capable of driving the 15k minimum DAC resistor ladder. With a gain of 1 configuration the external reference must be less than VCC - 1.5V. Voltage Output The rail-to-rail buffered output of the LTC1454 family can source or sink 5mA when operating with a 5V supply while pulling to within 300mV of the positive supply voltage or ground. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 40 when driving a load to the rails. The output can drive 1000pF without going into oscillation.
LTC1454/LTC1454L
APPLICATIONS INFORMATION
A Single Supply, 4-Quadrant Multiplying DAC The LTC1454 can also be used for 4-quadrant multiplying with an offset signal ground of 1.22V. This application is shown in Figure 2. The inputs are connected to REFHI B or REFHI A and have a 1.22V amplitude around a signal ground of 1.22V. The outputs will swing from 0V to 2.44V, as shown by the equation with the figure. Since the signal ground is around 1.22V, REFLO is offset above ground by using an LT1034CS8-1.2 as shown.
X1/X2 B CLR CLK DIN CS/LD CLK DIN LTC1454 CS/LD DOUT X1/X2 A VOUT A VOUT A
VOA/B = VIN - VREFLO GAIN
(
= VIN - 1.22 2.0
(
)
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)
W
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5V
0.1F VOUT B VCC REFHI B GND REFLO REFHI A REFOUT VCC LT1034CS8-1.2 VINA 1.22V 1.22V VINB 1.22V 1.22V 10k VOUT B
(
(
DIN - 1 +1 + VREFLO 4096
DIN - 1.0 + 1.22V 4096
)
)
1454 F02
Figure 2
9
LTC1454/LTC1454L
PACKAGE DESCRIPTION
0.300 - 0.325 (7.620 - 8.255)
0.009 - 0.015 (0.229 - 0.381)
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
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Dimensions in inches (millimeters) unless otherwise noted.
N Package 16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770* (19.558) MAX 16 15 14 13 12 11 10 9
0.255 0.015* (6.477 0.381)
1 0.130 0.005 (3.302 0.127) 0.015 (0.381) MIN
2
3
4
5
6
7
8
0.045 - 0.065 (1.143 - 1.651)
0.065 (1.651) TYP 0.125 (3.175) MIN 0.005 (0.127) MIN 0.100 0.010 (2.540 0.254) 0.018 0.003 (0.457 0.076)
N16 0695
LTC1454/LTC1454L
PACKAGE DESCRIPTION
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0 - 8 TYP
0.016 - 0.050 0.406 - 1.270 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Dimensions in inches (millimeters) unless otherwise noted.
S Package 16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 - 0.394* (9.804 - 10.008) 16 15 14 13 12 11 10 9
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1 0.053 - 0.069 (1.346 - 1.752)
2
3
4
5
6
7
8
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
S16 0695
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LTC1454/LTC1454L
TYPICAL APPLICATION
LTC1454: 4.5V TO 5.5V LTC1454L: 2.7V TO 5.5V OUTPUT B LTC1454: 0V TO 4.095V LTC1454L: 0V TO 2.5V
P
TO NEXT DAC FOR DAISY-CHAINING OUTPUT A LTC1454: 0V TO 4.095V LTC1454L: 0V TO 2.5V
RELATED PARTS
PART NUMBER LTC1257 LTC1446/LTC1446L LTC1450/LTC1450L LTC1451 LTC1452 LTC1453 LTC1456 LTC1458/LTC1458L DESCRIPTION Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, Reference Can Be Overdriven up to 12V, i.e., FSMAX = 12V Dual 12-Bit Rail-to-Rail Output DACs in an SO-8 Package Single 12-Bit Rail-to-Rail Output DACs with Parallel Interface Single 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V Single 12-Bit Rail-to-Rail Output VOUT Multiplying DAC, VCC: 2.7V to 5.5V Single 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V Quad 12-Bit Rail-to-Rail Output DACs COMMENTS 5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package 3V, Low Power, Complete VOUT DAC in SO-8 Package Low Power, Complete VOUT DAC in SO-8 Package, with Clear Pin LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 q (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
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X1/X2 B CLR CLK DIN
VOUT B VCC REFHI B
0.1F
LTC1454 GND LTC1454L CS/LD REFLO DOUT REFHI A REFOUT VCC LTC1454: 2.048V LTC1454L: 1.22V
1454 TA01
X1/X2 A VOUT A
1454lf LT/TP 0397 7K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1996

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